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Parallel computing is becoming an increasing cost-effective and affordable means for providing enormous computing power. Workstations are currently using parallel processing technology and will use it even more in the future. A large number of medium-priced multiprocessors are commercially available today. Numerous vendors of workstations are currently marketing multiprocessor-based workstations as well. More such powerful workstations will be available in the future. It should be noted that while it is relatively easy to build parallel machines whose peak performance will be thousands of MFLOPS and MIPS (adequate for future VLSI CAD requirements), it is extremely difficult to harness the computational power effectively to actually have the machines deliver all those MFLOPS and MIPS to the VLSI CAD user. Therein lies the challenge: design of good, efficient, parallel algorithms that can use the hardware resources to get the maximum performance.
This book will discuss the use of parallel processing for solving problems in a growing application area whose computational requirements are enormous: VLSI CAD applications. While numerous books exist on general parallel algorithms for regular matrix problems or graph theory problems, they are mostly theoretical in nature. This book will discuss practical parallel algorithms for shared memory MIMD, message passing MIMD, and SIMD parallel machines. The first two chapters provide a detailed introduction to the field of parallel computing: architectures, algorithms, and programming and forms the groundwork for writing parallel programs for parallel machines. The Chapters 3 through 9 deal with different CAD applications, and Chapter 10 provides a summary and a look at the future. The area of parallelizing compilers (that take sequential programs and produce parallel
Parallel Architectures and Programming
Placement and Floorplanning
Detailed and Global Routing
Layout Verification and Analysis
Circuit Simulation
Logic and Behavioral Simulation
Test Generation and Fault Simulation
Logic Synthesis and Verification
Conclusions and Future Directions